The World Wide Web Consortium has agreed to form a working group to draft an industry-wide recommendation on implementing Web services choreography, to enable Web services to better interact with each other for more automated transactions.
The Web Services Choreography Working Group, which will be co-chaired by Oracle Corp.’s Martin Chapman and Enigmatec Corp.’s Steven Ross-Talbot, at this juncture will consider two choreography proposals submitted to W3C. These include Hewlett-Packard Co.’s Web Services Conversation Language (WSCL) and Sun Microsystems Inc.’s Web Services Choreography Interface (WSCI). The WC3 effort is to be built on WSDL 1.2, according to W3C spokesperson Janet Daly. But a rival choreography proposal by Microsoft Corp., IBM Corp. and BEA Systems Inc., called Business Process Execution Language for Web Services (BPEL4WS), is not now being considered by W3C because it has not been submitted to W3C and lacks a royalty-free condition of its use, Daly said. This condition, required by W3C, means that authors of the proposal could not collect fees for use of the technology as a W3C recommendation.
Sun readying J2EE 1.4
Sun Microsystems Inc. officials recently presented a laundry list of technology and promotional efforts planned for the Java language, including the February release of Version 1.4 of J2EE (Java 2 Enterprise Edition), featuring integrated Web services support.
J2EE 1.4 officially integrates Web services support, including SOAP and WSDL functionality that many developers already have tacked on to Java, according to Mark Hapner, distinguished engineer for Java software at Sun, in Palo Alto, Calif. Web services backing is being added to J2EE via Sun’s JAX RPC (Java API for XML-based RPC).
Intel revamps future Itanium chip plans
Intel Corp. disclosed an updated road map for its Itanium 2 processor line last month, detailing work on future versions of the fledgling chip that should help keep the pressure on rivals Sun Microsystems Inc. and IBM Corp., according to an industry analyst.
Intel has previously said it plans to bring out a new 1.5GHz version of its Itanium 2 processor, code-named Madison, around mid-year and shortly follow that with the introduction of a more energy efficient Itanium 2 chip code-named Deerfield. The company has revealed it also plans to roll out a second version of the Madison chip in 2004 that boosts the Level 3 cache size from 6MB to 9MB.