TI to sample 65-nanometer chips in early 2005

Texas Instruments Inc. (TI) plans to sample a wireless product built with its 65-nanometer semiconductor manufacturing process technology in the first quarter of next year, the Dallas-based company said Monday.

Offering details of its 65-nanometer complementary metal oxide semiconductor (CMOS) process, the company said that it expects the new technology will reduce leakage power from idle transistors, such as when a cell phone is in standby mode, by a factor of 1,000.

In recent months, 90-nanometer processors have been introduced and rolled out in PCs and wireless devices. The smallest track or gap width on a chip surface is measured in nanometers. A lower nanometer measurement means that semiconductors can be made that are physically smaller, and they also are faster, more powerful and efficient because more transistors can be packed into the smaller space. For instance, TI says that its 65-nanometer process will allow integration of hundreds of millions of transistors supporting analog and digital function in system on chip configurations.

Sixty-five nanometers is roughly a thousandth of the width of a single human hair, which is about half the width of 90 nanometers. This means that the 65-nanometer CMOS process doubles the transistor density of 90 nanometers. TI’s 65-nanometer process uses dense embedded static RAM (SRAM) so that six transistors in a cell take up less than half a square micron with 1.5M bits fitting in a square millimetre. Such a small SRAM cell lets TI integrate large amounts of memory close to its processor cores, the company said.

Multimedia devices and high-end digital consumer electronics, such as wireless handsets and digital cameras, are pushing semiconductor makers to develop ever smaller chips that are faster and use less power more efficiently. TI is initially focusing its 65-nanometer efforts on wireless applications, with plans to introduce its SmartReflex dynamic power management technology at the 65-nanometer node in chips for that type of use. The technology monitors circuit speed and adjusts voltage to meet performance requirements of the device being used, boosting battery life and decreasing heat production, TI said.

The company plans to offer several “optimized 65nm recipes” for different products or applications by adjusting transistor gated length, threshold voltage, gate dielectric thickness or bias conditions, among other things, TI said. Its 65-nanometer design library will provide circuit designers with options across multiple different voltage transistors.

Three different ranges of 65-nanometer semiconductors will be offered. A low power option will be for portable devices such as 2.5G (generation) and 3G wireless handsets, digital cameras and audio players with multimedia functions. The midrange will support digital signal processing products and the company’s high-performance application-specific integrated circuit library for communication infrastructure products. A high-end version, which will have transistor gates as short as 29 nanometers, will support applications like Sun Microsystems Inc.’s next generation UltraSparc processor-based servers.

Although the industry has only just begun to see 90-nanometer semiconductors and products hit the market, the race to capitalize on the forthcoming 65-nanometer market has already started to get hot. Intel Corp. is working this year on its 65-nanometer technology, and Sony Corp. and its subsidiary Sony Computer Entertainment Inc. have joined forces with IBM Corp. and Toshiba Corp. Samsung Electronics Co. Ltd. also is working with IBM to develop techniques for making components that will use 65-nanometer and 45-nanometer CMOS process technology.

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