Intel: New chip process may change nets

Corporate and carrier networks are likely to be transformed by a new generation of processors built using a 90-nanometer manufacturing process, the smallest and fastest yet, Intel Corp. said Monday.

The chip giant expects to introduce its first 90-nanometer communications processors in the second half of 2003, around the same time it adopts the new process for PCs and server chips, underscoring the importance Intel now places on the infrastructure over which computers and other devices communicate. Intel also will begin producing its Prescott next-generation desktop PC chip with the 90-nanometer process in the second half of 2003, the Santa Clara, Calif. company said last week.

Sean Maloney, executive vice-president and general manager of Intel’s communications group, will lay out the company’s vision for 90-nanometer chips in networking on Monday, at the National Fiber-Optic Engineers Conference in Dallas.

Each generation of chip-making technology, which in recent years has moved from 0.18 micron (180 nanometer) to 0.13 micron (130 nanometer), allows for transistors with smaller gates. The new process can create one 90 nanometers wide, so it can pack two and a half times more transistors in a given space. That means smaller, less expensive and less power-hungry chips with twice the speed of current processors. It serves the needs of service providers and network administrators who want more capable hardware that takes up less space and requires fewer visits by technicians.

For chips that act as the brains of switches, routers, interface cards, cellular base stations and other network equipment, 90-nanometer represents a breakthrough, according to Tony Stelliga, director of advanced technology in the Intel Communications Group.

With the new process, Intel can fit six transistors into one square micron of space on a chip. Packing the parts that tightly means a networking chip can carry out 10,000 instructions per packet on a data stream of 1Gbps, Stelliga said. That kind of power lets the processor become a firewall, intrusion detection system and VPN (virtual private network) gateway. High-level functions like these in many cases today are still handled by standalone devices.

For example, the faster processors now will be able to defend a network device against DDoS (distributed denial of service) attacks, which are constantly evolving and becoming harder to track down, Stelliga said. Preventing the most sophisticated DDoS attacks now requires an awareness of the state of traffic over time, a large amount of quickly available memory, and up-to-date algorithms.

“You could simply never do a (denial of service prevention) function at a gigabit if you didn’t have 10,000 instructions per packet at your disposal,” Stelliga said.

Building those kinds of functions into a programmable network processing unit (NPU) allows for a device that can be reconfigured remotely to provide new services. For example, a metropolitan area network service provider could put a multiservice switch in the basement of a building and set up particular services for individual tenants without having to send out a technician or make a hardware change. One port could be used to provide data, fax or VoIP (voice over IP) services, along with the additional high-level features, as the customer required.

“The infrastructure market has never been agile” until now, Stelliga said.

The new manufacturing process also will let Intel build a single chip that can handle a wide variety of wireless technologies, such as Bluetooth, IEEE 802.11b and wide-area cell-based systems, Stelliga said. Intel will be able to integrate silicon germanium transistors into a CMOS (complementary metal-oxide semiconductor) chip made with the new process. Those silicon germanium components can condition the analogue signals that come in through an antenna or optical interface, converting them to a form that the CMOS chip can process.

Today, the analogue signals have to be conditioned by separate, dedicated chips. Putting that process directly on the chip wasn’t possible without the horsepower the new technology provides. This “mixed signal integration” could make cell phones and other wireless devices smaller, cheaper and more flexible.

Mixed signal integration also will help reduce the cost of optical interfaces by four times through integration that will bring the component down to three chips from about 10 chips, Stelliga said. For an equipment manufacturer, that could mean fitting 12 ports on a module that previously could have accommodated only four. The interfaces also will consume less power, solving the twin problems of real estate and electricity costs for equipment in carrier facilities.

To take full advantage of the increased chip density, Intel replaced parallel with serial technology for the links among chips, boards and racks. This replaces several slower connections with just a few fast connections. In addition to higher speed, that means less work to break up information and put it back together again, as well as savings in space and power.

Analysts questioned the significance of the 90-nanometer process in the evolution of network chips.

“This won’t be like a dam breaking,” said Joseph Byrne, an analyst with Gartner Inc. in San Jose. “We’re talking about points in a continuum, and it just becomes more cost-effective to implement new functions,” he added.

“I’m not aware of a particular application that is being enabled by the ability to process packets four times faster than you could in the previous generation. That’s not to say that you can’t do more,” Byrne said.

“It’s just a number,” said Linley Gwennap, president and principal analyst of The Linley Group, in Mountain View, Calif.

However, the mixed signal integration Intel described Monday may do a lot to shape wireless devices, Byrne said. It could open the door to future handheld computers with Bluetooth, wireless LAN and third-generation mobile data capabilities that are small and slim and have a long battery life, he said.

Gwennap also said the mixed signal integration could be significant.

“Being able to combine silicon germanium and CMOS on the same chip is something we haven’t seen before. It does allow for some pretty intriguing cost reduction and power reduction in any kind of device that has high-speed analogue signals, which is practically anything today,” Gwennap said.

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