Intel is sharpening its Jenga skills by stacking multiple chips onto a single package. Its new Lakefield hybrid processor announced June 10 stacks multiple layers on top of one another to save space and increase power efficiency.
Intel first detailed its Foveros 3D chip packaging technology in 2018. By stacking two logic dies and two layers of memory on top of one another, Intel was able to reduce the total die package to just 12mm x 12mm. Moving the memory on top of the processor also free up space that would otherwise be occupied by system memory. Manufacturers can either use the area to house additional features or create compact system designs.
System designers can choose between 4GB and 8GB LPDDR4X memory configurations.
The Lakefield processors come in Core i3-L13G4 and Core i5-L16G7 stock-keeping units (SKU). Both processors feature five cores: one performance core based on Intel’s “Sunny Cove” architecture, and four efficiency cores based on the “Tremont” core architecture. Processors based on the Sunny Cove architecture are typically used in Intel’s Ice Lake processors designed for mainstream performance mobile PCs, while the Tremont architecture is reserved for low-powered processor series like Intel Atom and Intel Pentium. Both architectures are designed on the 10nm node. Hyperthreading has been disabled on both SKUs to save power.
|Processor||Intel Core i3-L13G4||Intel Core i5-L16G7|
|Graphics||Intel UHD graphics||Intel UHD graphics|
|Graphics execution units||48||64|
|Max single-core turbo clock||2.8GHz||3.0GHz|
|Max all-core turbo clock||1.3GHz||1.8GHz|
|Memory||4267MHz LPDDR4X||4267MHz LPDDR4X|
The Core i3-L13G4 is tuned at 0.8GHz base frequency and 2.8GHz turbo frequency, while the Core i5-L16G7 sits at 1.4GHz base / 3.0GHz turbo. Aside from their processor frequency differences, the Core i5-L16G7 also has more robust graphics, coming with 64 execution units (EUs) as opposed to the Core i3-L13G4’s 48.
Since they’re are intended for power-efficient, mobile PCs, Lakefield processors have their TDP set at 7W for PL1 and 9.5W for PL2 during boost.
Intel first announced Lakefield and the Foveros 3D packaging in 2019. From the top, two DRAM layers stack on top of the compute die, and the compute die is in turn stacked on top of the base die with cache and I/O. They’re then stacked onto an interposer that sends data between the layers using a through-silicon vias (TSV).
Stacking chips creates more benefits than freeing up space on the motherboard. According to eeJournal, one of the greatest barriers to system-in-package design is the memory being too far away from the processor itself. By moving the memory chips directly onto the package, it reduces the length of traces between the processor and the memory chips, thus cutting down the latency. Reducing the trace length also reduces the power that’s required to drive them, further improving efficiency.
The first designs to feature the Intel Lakefield processors will be Lenovo’s ThinkPad X1 Fold and the Samsung Galaxy Book S.