Intel Corp. plans to introduce a major change in the architecture used to build its chips during its upcoming Fall Intel Developer Forum (IDF) in San Francisco.
The highlight of Chief Executive Officer Paul Otellini’s keynote speech on Aug. 23 will be the announcement of Intel’s “next-generation architecture,” which will arrive in the second half of 2006, said Rob Chapman, general manager for IDF, in a briefing earlier this week. The target date for its introduction coincides with the launch of previously announced processors that sources have said will use a common architecture based on power-friendly design principles.
Earlier this year, Otellini announced that Merom, Conroe and Woodcrest were the code names for Intel’s next generation of multicore processors slated for late 2006, but he declined to discuss them in detail. However, for some time Intel has been expected to base this generation of processors on an architecture inspired by its Pentium M notebook processor, which de-emphasizes clock speed and concentrates on managing power consumption.
The move appears to signal the end of the Netburst architecture, which has been the foundation of the Pentium 4 and Xeon chips for five years. That architecture was designed to let Intel steadily increase the clock speeds of its chips; however, the advent of the 90-nanometer process generation and the current leakage problems associated with that technology put an end to that strategy. As clock speeds go up, more power is needed to reach those speeds, and that power is more prone to leak out of transistors made with the current generation of chip-making equipment.
The Pentium M was designed to deliver top-notch performance while controlling the amount of power used to run the chip. Those design principles, combined with multiple processing cores on a single chip, will allow Merom, Conroe and Woodcrest to reach new performance heights without producing excessive heat.
Merom is a notebook chip, while Conroe is slated for desktops and Woodcrest for servers. Chapman declined to comment when asked if the Merom generation of chips would be the first to use the new architecture, but several sources familiar with Intel’s plans have identified these chips as the first. He also declined to discuss whether the chips will feature two processor cores or four.
More details about the next-generation architecture will be provided in a briefing for press and analysts following Otellini’s keynote on the 23rd, Chapman said.
Intel hosts the three-day IDF every six months to provide detailed information about upcoming products to the hardware engineers that design systems using Intel’s chips. The Santa Clara, California-based company also uses the show to announce major initiatives before an audience of press and analysts from around the world.
Otellini’s keynote, his first as Intel’s CEO, will be followed by presentations from the executive in charge of the Intel Mobility Group, Sean Maloney, on the notebook and wireless chip markets, and Digital Health Group leader Louis Burns. Burns will discuss some of the products and strategies under development by his newly formed group for one of the first times in public, Chapman said.
On the following day, Pat Gelsinger, senior vice president and general manager of Intel’s Digital Enterprise Group, will give an update on his division, which makes chips for desktops and servers used by corporations. Vice President and General Manager Don McDonald will appear after Gelsinger to talk about his digital home division, another key area for Intel’s product development teams.
As usual, Justin Rattner, head of Intel Labs, will close the conference with a peek behind the curtain of Intel’s research and development efforts. He is expected to discuss Intel’s 2015 Platform Initiative, an effort to develop what Intel calls self-managing and self-healing systems, Chapman said.