ISSCC: Intel talks up Madison, future chip designs

Intel Corp. will discuss the next-generation of its Itanium processor family and outline techniques developed for future integrated circuits at the International Solid State Circuits Conference (ISSC) this week in San Francisco.

Details about Madison, the successor to the current Itanium 2 processor, were first revealed last fall on the ISSCC Web site. Intel will provide more details in a paper expected to be presented Monday, said Nimish Modi, general manager of the Intel enterprise processor division.

Intel will offer the three models of the Madison chip with 3MB, 4MB, or 6MB of Level 3 on-die cache, Modi said. On-die cache allows the processor to store frequently accessed data close to the processor, improving performance. Madison will be available at 1.5GHz, and at two other clock speeds that have not yet been announced, Modi said.

The Madison chip is on schedule to be released in the middle of this year, Modi said. A follow-on version with up to 9MB of cache will come out in 2004 as a “product refresh,” he said.

Madison will be completely compatible with older Itanium processors, allowing system builders and users to insert the new chip without having to redesign the motherboard. Intel cited benchmarks that said Madison will result in a 30 per cent to 50 per cent increase in performance over the Itanium 2 processor for existing software.

The Santa Clara, Calif., company will release a low-power version of Madison, code-named Deerfield, by the end of 2003, Modi said. More details about Deerfield will be provided at the company’s Spring Intel Developer Forum, scheduled to begin Feb. 18 in San Jose.

Madison will consume the same amount of power as Itanium 2 (130 watts) despite the faster clock speed and increased cache through aggressive clock-gating techniques and a redesign of some of the circuitry, Modi said. Clock-gating is a method in which power is cut off to unused portions of a processor when that portion isn’t needed.

The company also spoke about the next processor past Madison, known as Montecito. Intel recently announced that Montecito will launch in 2005 with a dual-core processor, a technology used by other server processor companies such as IBM Corp. Modi revealed that Montecito will come with at least 18MB of L3 cache, double the amount of cache slated for the Madison product refresh in 2004. Each Montecito core will also have its own L3 cache, he said.

While Madison will be out on the market this year, Intel Labs is working on several technologies that won’t be used in the company’s products for several years, said Shekhar Borkar, an Intel fellow with Intel Labs.

The company will discuss this week several microarchitectures that Intel is designing to combat the obstacles of power dissipation and power leakage that are presenting challenges to Moore’s Law, he said. Moore’s Law, authored by Intel co-founder Gordon Moore, states that the number of transistors on a chip will double every two years.

Intel Labs is building several examples of what the company called special purpose hardware. These are low-power integrated circuits (ICs) that will be placed on the die to relieve the general-purpose processor of certain repetitive tasks that drain processing performance, Borkar said.

The company will discuss a 5GHz floating-point MAC (multiply accumulate) unit, which is key for multimedia applications, Borkar said. Floating-point units are ICs that specialize in solving large, complex mathematical problems.

Intel Labs has also developed a TCP (Transmission Control Protocol) offload engine that is built just to service network traffic, he said. This frees the general-purpose processor from the numerous instructions that need to be executed to process network traffic, and allows users to increase performance of the overall system with only a two-watt increase in power dissipation, he said.

The company will be able to design circuits with clock speeds up to 10GHz by using the multiphase clock generator. Multiphase clocks enable processors to execute multifunction operations during a single clock cycle, and can also stretch an operation over a single clock cycle.

Intel has also taken steps to address power leakage through the development of sleep transistors, which function like switches that are automatically turned off when the processor is not in use. This prohibits power from escaping the circuit, but requires small amounts of power in order to activate the switches. For that reason, the sleep transistors are only recommended for complex applications that require higher performance, where the power savings will be more evident, Borkar said.

The company will also present a paper at the conference detailing a multiprocessor bus architecture for four-way systems that allows data transfer rates of 6.4GB/sec., Modi said.

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