UPF chip designer tools in the works

Three chip designers are collaborating on tools for designing low-power chips, based on the Unified Power Format 1.0 standard, which was ratified last February.

Magma Design Automation Inc. of San Jose, Calif., along with Wilsonville, Ore.-based Mentor Graphics Corp. and Synopsys Inc. of Mountain View, Calif. announced this week they plan to make implementation and verification products for low-power integrated circuits.

The UPF standard, developed by Accellera Organization Inc. of Napa, Calif., is said to support lower power design flow from registered transfer level to silicon, and allow designed to user tool from more than two-thirds of the electronic design automation (EDA) marketplace at the same time.

UPF 1.0 defines the method for creating a supply network to supply power to each design element. It also specifies how individual supply nets interact with each other and how the logic functions are extended to support dynamic power switching to the logic design elements.

Would you recommend this article?

Share

Thanks for taking the time to let us know what you think of this article!
We'd love to hear your opinion about this or any other story you read in our publication.


Jim Love, Chief Content Officer, IT World Canada

Featured Download

Featured Articles

Cybersecurity in 2024: Priorities and challenges for Canadian organizations 

By Derek Manky As predictions for 2024 point to the continued expansion...

Survey shows generative AI is a top priority for Canadian corporate leaders.

Leaders are devoting significant budget to generative AI for 2024 Canadian corporate...

Related Tech News

Tech Jobs

Our experienced team of journalists and bloggers bring you engaging in-depth interviews, videos and content targeted to IT professionals and line-of-business executives.

Tech Companies Hiring Right Now