Intel shows off 65 nanometer memory cells

Intel Corp. has demonstrated working static RAM (SRAM) chips with transistors built using the company’s 65 nanometer process technology, the company announced Monday.

Microprocessors built using the technology will be ready in 2005, the Santa Clara, Calif., company said in a press conference. Intel uses SRAM chips to test out its process technology because the chips are easy to design and troubleshoot, but the transistors will be used on new versions of products such as the Pentium 4 or Xeon, said Mark Bohr, an Intel senior fellow and director of the company’s process architecture and integration.

Products built on Intel’s 90 nanometer process technology are expected to make their debut in the coming weeks. For the next generation of chips built at 65 nanometers, Intel will keep the strained silicon and copper interconnects used in 90 nanometer chips, Bohr said.

Strained silicon is a manufacturing technique in which a layer of silicon germanium is deposited on top of a silicon wafer. The atoms in each substance naturally seek to align themselves, which stretches the silicon, allowing more electrons to flow than was possible with just silicon.

Intel will also use eight layers of copper interconnects and a new low-k dielectric material on the 65 nanometer chips that reduces power consumption, Bohr said. A material’s “k” value refers to its ability to compress electrical fields, and a dielectric with a lower k value increases the speed at which electrons flow through a transistor.

The costs of moving to the 65 nanometer technology will be reduced by the ability to use much of the same lithography tools used to make the 90 nanometer chips, Bohr said. Intel will purchase some upgraded tools to help build some of the new structures, but most of the tools will remain the same, he said.

The 65 nanometer chips will be produced at Intel’s facility in Hillsboro, Ore,, and rolled out to the company’s other manufacturing plants over time, Bohr said.

Intel recently announced it was moving to a new high-k dielectric material as well as metal gates on its 45 nanometer process technology. The discovery of that material came too late to include in this process technology, Bohr said.

The high-k material is necessary at the 45 nanometer level to prevent current leakage caused by the extreme thinness of the chip’s structures at 45 nanometers, Intel said last month.