IBM Power for researchers, academia

IBM Corp. announced plans to provide free access for researchers and educational institutions to the specifications for its PowerPC 405 chip core. The move is yet one more way in which IBM is trying to widen the number of users of its Power processors.

The hope is that allowing third parties to experiment with the PowerPC chip core will result in more innovation around the technology. Cores are individual chip designs that developers can integrate with other designs to create custom chips.

The announcement comes after academics engaged in collaborative multicore processing research approached IBM to request more access to its Power architecture, the vendor said in a release issued late Wednesday.

The researchers included the Research Accelerator for Multiple Processors (RAMP), a project headed up by the University of California, Berkeley; Stanford University; the Massachusetts Institute of Technology; Carnegie Mellon University (CMU); the University of Texas at Austin; and the University of Washington. Its aim is to build a scalable, multiboard system based on field programmable gate arrays so researchers can experiment with building, programming and managing massively parallel systems of between 64 and 1,024 processors.

IBM plans to make the PowerPC 405 specifications available to researchers and academics via, the vendor consortium it set up just over a year ago.’s mission is to promote the Power architecture. Its members include Cadence Design Systems Inc., Chartered Semiconductor Manufacturing Ltd., Novell Inc. and Red Hat Inc. IBM is positioning the Power architecture as suitable for all systems, from handheld devices up to supercomputers and has been licensing the technology to third parties.

Last week, Sun Microsystems Inc. announced its intention to publish the specifications for its new UltraSparc T1 chip under a program called OpenSparc. Sun positions its UltraSparc-based servers against IBM’s Power5+-based servers.

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