It’s enough of a challenge to engineer city highways. Imagine that kind of planning on a canvas that’s only 10 mm by 10 mm.
That’s the basic challenge for physical chip designers who have been known to use whiteboards to draw and plan the blueprint for circuit design on ASIC and system-on-chips (SoC). A Kanata, Ont.-based company is trying to get the designers to throw out their whiteboards and erasers forever.
“We want to be a desktop engineering tool for physical chip design,” said president of Icinergy Software Comp., Scott McLellan. “We want to be positioned like the calculator, where there is a very quick answer back, though it’s a bit more complicated than the calculator.”
McLellan is shooting for that positioning with the company’s flagship product, the SOCarchitect, which captures the physical aspects of design with logical connectivity at the architectural level and creates a pre-RTL spreadsheet view of the design.
“One of the things our tool does is allows you to bring in existing information, create these blocks on the fly and add connectivity,” he said. “It allows for more detail and to test it and to move them around and, in this case, you would be continuously wiping of the whiteboard.”
Jeff Romanko, principle engineer at Kanata, Ont.-based Tropic Networks said the Icinergy tool has saved the engineers at Tropic a lot of time and money up front so far.
“We use the tool for architectural planning of the fiscal implementation,” he said. “We use the tool in the floor-planning mode to place all the macro-cells and plan the data-path between them and try to determine if we are going to fit on the appropriate die-size and not have any problems with congestion.”
Romanko said he particularly likes the simplicity of the tool, and that it doesn’t require a lot of technology information or set-up information up front.
“You input the perimeters and you just need data sheets,” he said. “We can play different technologies off one another and figure out the pros and cons of each.”
The only change Romanko would make would be to have a “light version” of the tool.
“They have a lot of functionality in there that we currently don’t use and we only use a small set of the planning features,” he said. “We would like a cheaper version that had fewer features.”
Icinergy, which sells 60 per cent of its wares in the U.S., plans for the next upgrade to have the full suite of tools for timing purposes, according to McLellan.
“Time enclosure is an important part of overall design because, when you get to the end, all the chips have to synchronize and talk to each other, and if the timing isn’t right, it won’t function,” he said. “So we have built into our features the ability to do a timing budget at the architectural stage and measure it against the synthesis stage and then measure that budget post-synthesis as well so that you are always comparing the budgeted to the amount estimated.”
But Dean McCarron, president of Mercury Research in Scottsdale, Ariz., said that while Icinergy’s offering is valid, it is anything but new.
“They are saying they are like the one-stop shop, but in a lot of environments, you are faced with one of two paths with this,” he said. “Path number one is that you pick a company and that company will have all of its own blocks but may not have any third-party blocks. What you end up doing is that you look through a lot of different companies to find the one that has the most blocks that you need, then you custom-design the rest.”
The other option, he said, is to go out and find all the individual suppliers and cutting a contract with each of them.
As for expunging the whiteboard, McCarron said there are two ways to look at that as well.
“Realistically, the whiteboard discussion will still be there, and, also realistically, no one does design on a whiteboard anymore,” he said, explaining that only the very rough first ideas for design are ever done manually now.
